1. Field of the Invention
The present invention relates to circuits of semiconductor devices, and more particularly, to an internal voltage generating circuit for supplying a stabilized power source to the semiconductor device.
2. Description of the Related Art
Generally, as miniaturization of semiconductor devices proceeds, an electrical field stress applied to a unit cell frequently exceeds a tolerance limit, thereby greatly affecting the device lifetime. That is, standard operating voltage conditions maintain the operating voltage substantially equal to that used in the past, depending on the circumstances of the entire system, even though the operating voltage conditions should be readjusted to comply with the miniaturization of the device. Thus, the reliability of the unit cells is degraded.
A conventional semiconductor memory device, for example, uses an internal voltage adapted to characteristics of the miniaturized products, where an internal voltage is typically lowered from an external voltage inputted from the outside. In the following background description, internal voltages of conventional semiconductor memory devices will be described with respect to FIGS. 1 through 3, including several problems and disadvantages thereof.
FIG. 1 is a schematic block diagram illustrating a conventional internal voltage generating circuit. Referring to FIG. 1, the conventional internal voltage generating circuit includes a reference voltage generator 10 and an internal voltage driver 20. The reference voltage generator 10 receives an external voltage Vcc to generate a reference voltage Vref, and the internal voltage driver 20 compares the reference voltage Vref with an internal voltage IVC fed back to output the internal voltage IVC following the reference voltage Vref.
FIG. 2 is a circuit illustrating the reference voltage generator and the internal voltage driver of FIG. 1. Referring to FIG. 2, resistors R1, R2 and N-type CMOS transistor NM1 are coupled in series between the external voltage Vcc and ground voltage Vss in the reference voltage generator 10. A gate of the N-type CMOS transistor NM1 is connected to a node NO1 between the resistors R1 and R2, the reference voltage Vref being generated form the node NO1. A P-type CMOS transistor PM1 is coupled between the node NO1 and the ground voltage Vss, in which a gate is connected to a drain node NO2 of the N-type CMOS transistor NM1.
Thus, as the external voltage Vcc is changed, the level of the reference voltage Vref is also changed, thereby generating the reference voltage Vref at a certain level even though the external voltage Vcc increases over a specific level. Further, the internal voltage driver 20 includes a comparator DA1 and a driving P-type CMOS transistor DPM1. The comparator DA1 includes a well-known differential amplifier, and compares the reference voltage Vref generated from the reference voltage generator 10 with the internal voltage IVC fed back from the output stage to output a comparison signal. Then, low level of the comparison signal is outputted if the reference voltage Vref is higher than the internal voltage IVC, otherwise high level of the comparison signal is outputted.
The driving P-type CMOS transistor DPM1 responds to the comparison signal and controls the external voltage Vcc to output the internal voltage IVC. The internal voltage driver 20 causes the internal voltage IVC to follow the reference voltage Vref by comparing the reference voltage Vref with the internal voltage IVC fed back, to decrease the output voltage if the internal voltage IVC is higher than the reference voltage Vref, but to otherwise increase the output voltage.
However, since the conventional internal voltage generating circuit generates the internal voltage IVC according to a level of the reference voltage Vref provided by the reference voltage generator 10, the level of the internal voltage IVC is not maintained constant when the external voltage Vcc is varied or when the extent of the operating power source is wide.
FIG. 3 is a graph illustrating an initial operating characteristic of the conventional internal voltage generating circuit of FIGS. 1 and 2, and indicated generally by the reference numeral 30. The internal voltage IVC has a characteristic that is increased according to the external voltage Vcc until an initial certain specific voltage, and at a setting voltage, tends to maintain a constant and stable voltage level independent of increment of the external voltage Vcc. In FIG. 3, the horizontal axis represents the external voltage while the longitudinal axis represents the internal voltage. The conventional internal voltage generating circuit, however, generates the internal voltage IVC having a certain variation gradient compared with an ideal internal voltage CVC that is uniform at a setting voltage. In addition, since the internal voltage driver 20 includes a transistor and a resistor, the internal voltage IVC generated from the conventional internal voltage generating circuit has a certain variation gradient that is substantially proportional to the external voltage Vcc.
Accordingly, the conventional internal voltage generating circuits suffer from the following problems and disadvantages: 1. When the external voltage is fluctuated, the reference voltage generated from the reference voltage generator is changed according to the external voltage, which also increases the variation gradient of the internal voltage that follows the reference voltage. Thus, the internal voltage acts as noise in the internal circuits of the semiconductor device requiring a stabilized power source, thereby causing a part of the circuit to be out of order and/or shortening the service life of the circuit.